The present invention relates to a semiconductor cell library for use in a layout process of a semiconductor integrated circuit and, more particularly, to a semiconductor cell library having flexible cell widths.
Semiconductor integrated circuits are designed and fabricated by first preparing a schematic diagram or hardware description language (HDL) specification of a logical circuit in which functional elements are interconnected to form a particular logical function. The schematic diagram or HDL specification is synthesized in to cells of a specific cell library. Each cell corresponds to a logical function unit which is implemented by one or more transistors that are optimized for the cell. A typical cell library may have several identical cells for each logical function unit, with each cell having a different, predetermined output drive strength. Higher drive strength is often achieved by placing additional drive transistors in parallel with one another within the cell. The logic designer selects the cells according to the number of loads that are attached to the cell, as well as the estimated interconnection required for routing.
The cells in the library are defined by cell library definitions. Each cell library definition includes cell layout definitions and cell characteristics. The layout definition includes a layout pattern of the transistors in the cell, geometry data for the cell""s transistors and cell routing data. The cell characteristics include a cell propagation delay and a model of the cell""s function. The propagation delay is a function of the internal cell delay and the output loading of the cell.
Most cell libraries have cells that conform to a single cell height to allow abutment of adjacent cells into rows without creating design rule violations. The cell height is selected to achieve a desired balance between transistor performance and density for the integrated circuit. If the cell height is short, the transistors in the cells are smaller and have less drive strength. However, the rows of cells can be place closer together (i.e., at a smaller row pitch). This allows more transistors to be placed in a given area. Thus, a short cell height provides higher density, with lower performance. If the cell height is tall, the transistors in each cell are larger and have greater drive strength. However, the rows of cells must be placed farther apart such that fewer transistors can be placed in a given area. Thus, a tall cell height provides lower density, with higher performance. As a result, a single library of cells is often a compromise between performance and density.
Some application specific integrated circuit (ASIC) suppliers have provided multiple cell libraries, with each cell library being tuned to a specific performance and density. However, this increases the resources and time required to support the cell libraries. Improved cell libraries are desired that provide more optimal support of both high density and high performance.
The semiconductor cell library of the present invention includes a plurality of semiconductor cell definitions. At least one of the semiconductor cell definitions includes a base cell and at least one derivative cell. The base cell has a logical function and includes a base cell layout pattern of transistors with at least one diffusion region. The derivative cell has the same logical function as the base cell and includes a derivative cell layout pattern of transistors with at least one a diffusion region. The diffusion region of the derivative cell layout pattern is expanded in one dimension outwardly from a geometric center of the layout pattern relative to the diffusion region of the base cell layout pattern.
Another aspect of the invention relates to a method of forming a layout definition of a semiconductor integrated circuit. The method includes selecting cells from a cell library, which has at least one base cell and at least one corresponding derivative cell having an identical logical function as the base cell. The base cell and the derivative cell each include a layout pattern. The layout pattern of the derivative cell has a wider transistor geometry than the layout pattern of the base cell. The selected cells are arranged in a semiconductor layout pattern and interconnections between the arranged cells are routed. Loading of the arranged cells is determined based upon the routed interconnections.
Another aspect of the present invention relates to a semiconductor cell library having a plurality of semiconductor cell definitions. At least one of the semiconductor cell definitions includes a base cell definition and a derivative cell definition. The base cell definition has a logical function and a base cell layout pattern of transistors. The derivative cell definition has the same logical function and a different transistor geometry as the base cell definition.